Reduced Instruction Set Computing (RISC) is a CPU design concept that seeks gains in power as a trade-off for simplified instructions. This design philosophy is directly opposed to Complex Instruction Set Computing (CISC), which is the basis of the x86 style processors of the vast majority of home PCs and laptops.
The construction of the RISC processor is such that performance is the priority, rather than raw power. When RISC and CISC were developed, the bottleneck of microprocessors was power, meaning that CISC won out and efficient, performance-oriented chips were used less and less. RISC came back into vogue when the need increased for chips that make efficient use of portable battery power.
Since the instruction set is so simple, that is, one instruction per cycle, RISC processors tend to be better used for simple and repetitive logic operations. CISC processors are truly "general purpose," meaning that they can pipeline multiple instructions at once without a preference for simpler or more complex applications. RISC processors need to be programmed in a very particular fashion.
The performance orientation of the RISC architecture is due to its simple and efficient instruction set. This simplicity means that RISC processors are easier to design and inexpensive to produce, making them ideal for purpose-built and cheap computing machines that execute repetitive instructions.
Long Instruction Strings
RISC processors can be adapted to run CISC style instruction strings, but they are incredibly inefficient at doing so. Since a RISC processor can only handle one instruction string at a time, code needs to be more compartmentalised and, therefore, more complicated.